The air gap flux and the rotor speed are detected by processing the signal obtained from the summation of the stator phase voltages, Vs3. The DSP performs the integration of the third harmonic voltage signal to derive the third harmonic flux. In order to detect the rotor speed the signal Vs3 is processed by a switched capacitor band-pass filter (SCF), whose central frequency can be tuned over a wide range (from about 20 Hz to 4 kHz). The output of the filter is a variable amplitude sinusoidal wave. This wave has the same frequency as the rotor slot ripple . Two options are to detect the frequency of the SCF output signal: a Phase Locked Loop or a frequency to voltage converter (FVC).
5.3.dos. Profession Programmable Entrance Arrays (FPGA)
A remarkable applying of DSPs or FPGAs is the sensorless handle to have high-speed applications in accordance with the delivery out-of PWM handle schemes, that are categorized while the unipolar and bipolar methods [24,51]. Depending on the PWM method made use of the manage strategy could potentially cause a good commutation reduce inside high speed programs since the PWM changing together with inverter commutation can’t be done separately. If the commutation quick try synchronized with the avoid of one’s PWM modifying several months finest commutation occurs having one delay. But once the commutating immediate utilizes new rotor position they doesn’t generally correspond toward end out of PWM several months and you can undesired commutation impede was put. This dilemma might be beat by the controlling the current and you may frequency separately by DC hook current manage system. So it manage are going to be accompanied having fun with a great DSP otherwise FPGA built high speed sensorless control arrangement .
Typical high speed programs in which PWM processes applies are electronic videos drive (DVD) spindle possibilities, in fact it is then followed playing with good FPGA, such as the Altera Bend EPF6024AQC240-3 . This new operator comes with one or two chief pieces: the brand new PWM age group routine plus the strength device manage circuit. Figure 23 suggests the machine, having its a beneficial FPGA, a good BLDC system, therefore the related resource and you can feeling circuits . Only critical voltages off around three phase is tested and you may given towards brand new FPGA controller to calculate new commutation instants. The program causes significant reduction of conduction losses and you can electricity usage, which is some essential short energy BLDCM Country dating site drives run on power supply and/otherwise that have restricted dissipation space.
5.3.step 3. Microprocessors (MP)
The lowest-cost sensorless control program to own BLDC vehicles will be implemented when the rotor updates info is derived from the filtering singular system-terminal-voltage, which leads to tall loss in elements matter of feeling routine. Since conveyed into the Shape 9 , just two of the about three state-windings was happy at the same time, therefore the 3rd stage was discover during the change episodes ranging from the good and you may negative apartment segments of one’s straight back-EMF . Hence, each of the motor critical voltages contains the back-EMF guidance which can be used to help you derive brand new commutation instants.
Cost saving is further increased by coupling the position sensing circuit with a single-chip microprocessor or DSP for speed control. Figure 24 shows a block diagram of the position detection circuit based on sensing all three motor terminal voltages for a BLDC motor. Each of the motor terminal voltages, referred to as the negative DC bus rail VA‚, VB‚ and VC‚ are fed into a filter through a voltage divider of a resistor network. This removes the DC component and high frequency contents that result from the PWM operation. The phase information is extracted from the back-EMF. The correction is based on measuring the elapsed time between the last two zero-crossing instants and converting it to frequency. This operation is achieved when the filtered voltage, VA”, is passed to a comparator to detect these zero-crossing instants, which are further sent to a microprocessor for phase-delay correction and generation of commutation signals. The microprocessor produces gate control signals for the inverter and may perform closed speed control with the motor speed information measured by the frequency of the detected signals .